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lpe questions

    process parameters for rc extraction can be found on hjtc's website. simply login into the tds account and go to design rule/document type category. parameters (e.g. ild, imd, thickness, dielectrics, min width and min spacing for each layer) can be found at categories: "electrical design rule", "interconnect capacitance model" and "topological layout rule".

    the support lists of lpe tools are shown as the following table. nautilus is not supported due to lack of vendor's support. dracula and star-rc are not recommended due to accuracy concern. however, hjtc still support dracula and star-rc.


    tool name


    star-rc; starrc-xt; arcadia


    draculalpe; hyperextract; assura; fire and ice

    mentor graphics

    xcalibre / xrc



    add the following commands under the description and operation blocks of the file will have dracula take the mos parameters.

      parset ichi area peri
      element mos[n] ngate poly nsd pwell
      element mos[p] pgate poly psd nsub
      lextract ichi psd by node pdiff
      lextract ichi nsd by node ndiff
      attach mos[p] pdiff
      attach mos[n] ndiff.

    the above figure shows two transistors in series, and they share the same diffusion for the source and drain. with dracula, a "nrx-extract" command can extract resistance values of both source and drain of the mos. the mos parameters in the output spice net_list will include l, w, ad, pd, as, ps, nrs, and nrd. the internal calculation function is described in chapter 11 of the dracula reference. users could also define their own parset to extract the area and perimeter of mos source/drain with their own equations.

    first, find the values of ca and cf in the spec document "electrical design rule", then add the following commands with both values on and respectively under the operation block:

      parasitic cap[xx] ngate poly ndiff
      parasitic cap[xx] pgate poly pdiff

    since hyperextract supports planar dielectric structure only, hjtc uses planar approach to implement conformal dielectric structure. the errors of planar approach are less than 5%.

    wee stands for wire edge enlargement. any effect (from manufacturing behaviors) that causes the real dimension not equal to the drawing is known as wee. bias, dishing, erosion, trapezoid shape are included.

    currently, only few rc extraction tools support wee effect. some lpe files on hjtc website include the wee factor. please read the header of command file for reference. you can contact hjtc for information in detail.

    cell level extraction will only extract the routing layers exclude the cells, transistor level extraction will extract parasitic rc down to the device level. if customers put the standard cells in the layout and already know the value of the cells, they could use the cell level extraction flow.

    currently only few tools claim they can do the l extraction (called rlc extraction tool), and most of the rc extraction tool vendors set the l extraction as their milestone.

    we will try to find out the possible causes of differences: the measurement error, process file typo, rc extraction tool accuracy issues or if the process documents is out of date. once the cause is determined, we will feedback the data to the corresponding department and solve the problem.

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